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Aeroflex Pumps Up Speed and Gate Count With Radhard FPGA

The new UT4090 FPGA is targeted to withstand total dose of 30 krads(Si) tested to MIL-STD-883 Method 1019.

Colorado Springs - Feb. 16, 2001
Aeroflex UTMC has developed a Field Programmable Gate Array (FPGA) that is radiation hardened for low-earth orbit and launch applications. The new UT4090 RadHard FPGA features 90,000 usable PLD gates, data path speeds of 200 MHz, embedded SRAM and is targeted for QML Q and T compliance.

The new UT4090 FPGA is fabricated on 0.35�m four-layer metal CMOS process to maximize speed and reduce power. While the part is manufactured on a commercial line, Aeroflex UTMC uses proprietary design techniques to alleviate single-event latch-up and improve SEU that typically prevents a commercial part from functioning in a radiation environment.

This FPGA is targeted to withstand total dose of 30 krads(Si) tested to MIL-STD-883 Method 1019. An Aeroflex UTMC designed flip-flop eliminates the need for triple mode redundancy (TMR). The SEL design target is LET > 128MeV-cm2/mg.

Aeroflex UTMC uses QuickLogic Corporation's licensed ESP (Embedded Standard Products) technology for the UT4090, providing a proven high performance architecture coupled with a robust development environment. QuickLogic is a pioneer in the FPGA semiconductor and software tools field.

Software support for the UT4090 is available from QuickLogic using their production proven QuickWorksTM package. QuickWorks provides an integrated framework supporting design entry via schematic capture, VHDL or Verilog, HDL synthesis, simulation, static timing analysis and place and route. The part is 100% routable with full utilization and complete pin-out stability.

QuickLogic's patented variable-grain logic cells provide high performance. To program the UT4090, DeskProTM software and DeskFabTM device programmer are available from QuickLogic.

The part interfaces with both 3.3 and 5 volt devices, and is PCI compliant with 3.3V and 5V busses. Advanced I/O capabilities include full JTAG boundary scan and registered I/O cells with individually controlled clocks and output enables.

The UT4090's 90,000 usable PLD gates are organized as 1,584 logic cells. In addition, 22 dual-port RAM modules provide a total of 25k bits of dedicated SRAM in a variety of configurations. This embedded SRAM is fast and efficient for FIFO, RAM, and ROM functions. Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules.

"Current and next generation satellite avionics and payloads need high-performance, deep sub-micron design solutions and options, particularly programmable logic with soft and hard IP cores," said Anthony Jordan, director of standard products for Aeroflex UTMC.

"We're responding with leading-edge RadHard solutions adapted from the commercial world. Our emphasis is, and will remain, reliability, hardness and high-performance."

"The UT4090 is Class Q and T certified," continued Jordan. "Aeroflex UTMC's goal with Class T is to rapidly inject leading edge, high performance, commercial product into the space community.

"This is our sixth Class T product since DSCC certification 15 months ago. Our new partnership with QuickLogic continues our commitment to bring leading edge technology to the space community."

"The UT4090 is just the first of many RadHard FPGA products to come from Aeroflex UTMC. We'll follow the 0.35�m product with a 0.25�m CMOS technology within the next 18 months."

The UT4090 is packaged in a 208-pin Cerquad flatpack and is available to Standard Microcircuit Drawing 5962-00533. The SMD greatly simplifies the procurement and allows Aeroflex UTMC to deliver product off-the-shelf, eliminating the costly paperwork of source control drawings. Prototypes are available in 2Q01 with production delivery expected to start in 3Q01.

Prices for the RadHard UT4090 FPGA start at $3,500.

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